The present invention relates to a pipelined SIMD-Systolic array processor and its methods. Especially, the present invention uses a way which combines both the broadcasting and the systolic structures to connect multiple pipelined processing elements together. Totally, the present invention accomplishes the design of an array processing architecture, which can process multiple data stream with single instruction stream, and its related computing methods. Moreover, the present invention can be applied to the design of parallel computers, video image processors, and digital signal processors. Meanwhile, the present invention can manipulate data transferring and shifting more efficiently, and also can be implemented on single VLSI chip. Thus, the present invention is full of practicability.